1. Field of the Invention
The present invention relates to the field of complementary-metal-oxide-silicon (CMOS) latch circuits; more specifically, it relates to a method of reducing the sensitivity of a master-slave flip-flop to radiation induced soft error events.
2. Background of the Invention
As geometries and operating voltages of advanced semiconductor devices and integrated circuits decrease, integrated circuits become more susceptible to temporary upsets in stored data (soft errors) caused by exposure to radiation. Radiation includes radiation due to high-energy atomic particles of either cosmic or terrestrial origin. High-energy particle collision with silicon atoms of the semiconductor substrate create electron-hole pairs that cause charge to collect within the circuit that takes time to dissipate. In particular, flip-flop circuits are especially vulnerable because it is impractical to apply error correction coding to a flip-flop (as would be applied to a memory circuit, for example) because flip-flops do not utilize the formal logical structure of words and bits. A soft error event in a flip-flop essentially builds charge on a storage node of the flip-flop. This charge must be dissipated to prevent an upset.
The sensitivity of a flip-flop circuit to a soft error event may be best understood by reference to FIG. 1. FIG. 1 is a schematic circuit diagram of a related art flip-flop circuit. In FIG. 1, flip-flop 100 includes a master latch 105 and a slave latch 110. Master latch 105 includes first and second inverters 115 and 120, first and second AND gates 125 and 130 and first and second NOR gates 135 and 140. Slave latch 110 includes third and fourth AND gates 145 and 150 and third and fourth NOR gates 155 and 160.
In master latch 105, a DATA signal is coupled to a first input of first AND gate 125 and through first inverter 115 to a first input of second AND gate 130. A CLK signal is coupled through second inverter 120 to a second input of second AND gate 130 to a second input of first AND gate 125. The output of first AND gate 125 is coupled to a first input of first NOR gate 135 and the output of second AND gate 130 is coupled to a first input of second NOR gate 140. The output of first NOR gate 135 is coupled to a node A and the output of second NOR gate 140 is coupled to a node B. Node A is coupled to a second input of second NOR gate 140 and node B is coupled to a second input of first NOR gate 135. A master latch output signal Qm is developed at node B and a master latch output signal QmN is developed at node A.
In slave latch 110, node A is coupled to a first input of third AND gate 145 and node B is coupled to a first input of fourth AND gate 150. The CLK signal is coupled to a second input of third AND gate 145 and to a second input of fourth AND gate 150. The output of third AND gate 145 is coupled to a first input of third NOR gate 155 and the output of fourth AND gate 150 is coupled to a first input of fourth NOR gate 160. The output of third NOR gate 155 is coupled to a node C and the output of fourth NOR gate 160 is coupled to a node D. Node C is coupled to a second input of fourth NOR gate 160 and node D is coupled to a second input of third NOR gate 155. A slave latch output signal Qs is developed at node C and a slave latch output signal QsN is developed at node D.
When the CLK signal is low, a new data signal from DATA is xe2x80x9cclockedxe2x80x9d unto master latch 105. Master latch 105 is in the transparent phase. During the transparent phase, nodes A and B are immune to a soft error event because the DATA signal will correct an upset in master latch 105 during this time. Similarly, when the CLK signal is high, data in master latch 105 is xe2x80x9cclockedxe2x80x9d unto into slave latch 110. Slave latch 110 is in the transparent phase. During the transparent phase, nodes C and D are immune to a soft error event because data in master latch 105 will correct an upset in slave latch 110 during this time. However, when master latch 105 is not transparent a soft error event that changes the data on nodes A and B cannot be corrected because the DATA signal is xe2x80x9clockedxe2x80x9d out. Upon the next clock cycle, incorrect data will be xe2x80x9cclockedxe2x80x9d into or out of slave latch 110.
Techniques to reduce the sensitivity of flip-flop circuits include: increasing device sizes (which increases capacitance and thence reduces speed) and implementing redundancy. Both these solutions require increased silicon area and more power which are counter productive to the original goals of smaller size and lower voltage that led to the soft-error sensitivity originally.
Thus, an improved technique is needed for reducing the sensitivity of flip-flop circuits to radiation induced soft error events.
A first aspect of the present invention is a flip-flop circuit comprising: a master latch circuit; a slave latch circuit coupled to the master latch circuit; and a correction circuit for increasing an amount of charge that can be absorbed by the master latch circuit in response to a soft-error event when the slave latch circuit is in a transparent phase and when both the master and slave latch circuits are storing the same data.
A second aspect of the present invention is a master-slave flip-flop circuit comprising: a first latch circuit having input terminals for receiving and latching a data signal and for receiving a clock signal and having output terminals providing first latched data signals in response to a first state of the clock signal; a second latch circuit having input terminals coupled to the output terminals of the first latch circuit for receiving and latching the data signals and having output terminals providing second latched data signals in response to a second state of the clock signal; a correction circuit coupled between the output terminals of the second latch circuit and the output terminals of the first latch circuit, the correction circuit operable to apply, from the output of the second latch circuit, the latched data signals of the second latch circuit to the output of the first latch circuit when the first and the second latched signals are the same and the clock signal is in the second state.
A third aspect of the present invention is a master-slave flip-flop circuit comprising: a first latch circuit having input terminals for receiving and latching a data signal and for receiving a clock signal and for providing first latched data signals to a set of nodes in response to a first state of the clock signal; a second latch circuit coupled to the set of nodes for receiving and latching the data signals and having output terminals providing latched data signals in response to a second state of the clock signal; a low node correction circuit coupled between the output terminals of the second latch circuit and the set of nodes, the correction circuit operable to apply data signals from the output of the second latch circuit to low nodes of the set of nodes when the first and the second data latched signals are the same and the clock signal is in the second state. The third aspect of the present invention further includes a high node correction circuit coupled between the output terminals of the second latch circuit and the set of nodes, the correction circuit operable to apply data signals from the output of the second latch circuit to high nodes of the set of nodes when the first and the second latched data signals are the same and the clock signal is in the second state.